Design and ESD protection of wideband, radio frequency integrated circuits in CMOS technologies.
Author: Karan Singh Bhatia
This work focuses on the design and electrostatic discharge (ESD) protection of wideband integrated circuits operating at frequencies up to 10 GHz. At these high frequencies, the shunt capacitance of ESD protection structures corrupts the termination impedance of the input/output (I/O) circuit. This reduces power transfer into and out of the circuit, increases noise figure and signal distortion, reduces gain and bandwidth, and adds to intersymbol interference in backplane channels. In other words, the performance of radio frequency (RF) I/O circuits can be severely degraded with the implementation of ESD protection.;In order to mitigate the undesirable effects ESD protection has on these I/Os, improvements must be made to the ESD device structures themselves as well as the I/O circuit topology chosen. In this work, layout optimization of ESD diodes in terms of metal routing and diode diffusion geometry in 180-nm (BiCMOS) and 90-nm (CMOS) process technologies is performed to lower the parasitic capacitance of these structures, while maintaining an acceptable current handling capability and on-resistance. In addition, the testing methodology for the characterization of these devices is described.;In addition to lowering the capacitance of the ESD devices themselves, this work also researches possible wideband circuit topologies that are amenable for ESD protection. However, most of these wideband topologies utilize large amounts of die area, thereby increasing manufacturing cost. Here, an ESD-protected CMOS low-noise amplifier (LNA) for 3-10 GHz ultra-wideband (UWB) applications is presented. The LNA exhibits a 4.25-kV ESD protection level along with an S21 of 15 dB and a noise figure of 6 dB across the entire UWB band. The LNA presented here utilizes only two inductors for die area minimization and dissipates 7.9 mW of power from a 1.8-V supply.;Finally, the work concludes with a summary of the design of a 6.25-Gb/s serial I/O transceiver for backplane communications that implements error correction coding to reduce equalization power and transmitter output swing. The design of the transmit driver with pre-emphasis equalization, receiver amplifier, and voltage controlled oscillator is described. The I/O transceiver is fully ESD-protected with an expected 2-kV human body model failure threshold.